1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory having a two-storied gate of a floating gate and a control gate, and methods of driving, operating, manufacturing this memory.
2. Description of the Prior Art
FIG. 26 is a diagram showing a memory cell array configuration in a non-volatile semiconductor memory such as a conventional flash memory, and illustrates a NOR flash memory. In FIG. 26, WLmxe2x88x921 to WLm+1 designate word lines; BLnxe2x88x921 to BLn+1 designate bit lines; and SL designates a source line.
First, an over-erased condition in the flash memory will be described.
In an array architecture called NOR or DINOR-type in memory cells, there is a difficulty that when there exists a cell in which a threshold voltage Vth (hereinafter, just referred to as Vth) is in a depletion state, i.e. Vth less than 0 on the same bit line, Vth measurements of the all cells on that bit line cannot be carried out. For example, when the Vth of a cell corresponding to BLn/WLm surrounded by circle A in FIG. 26 is in a depletion state, even if the threshold voltages Vths of the other cells on the BLn line are in an enhanced condition (Vth greater than 0), the Vths of the other cells cannot be measured since all the Vths become 0 V or less due to an effect of the cell of BLn/WLm.
Hence, when a Vth distribution in the aforementioned array configuration is checked, cells in proportion to the number of cells on the same bit line are determined to have a value of Vth less than 0 in a Vth distribution of over-erase failure as shown in FIG. 27. The cells in a depletion condition may cause upon the extraction of electrons from the floating gate of a flash memory when some electrons are accidentally over-extracted.
This phenomenon is described as an erratic over erase in xe2x80x9cA Self-Convergence Erase for NOR Flash EEPROM Using Avalanche Hot Carrier Injectionxe2x80x9d (Document 1: IEEE Trans. Electron Devices, vol.43, p.1937, 1996, S. Yamada et al.).
A write back of the threshold voltage Vth of an over-erased cell will be next described. The write back herein referred to is writing back the Vth of the erased cell to an enhancement condition. Various methods of performing the write back are disclosed in the prior art.
First, a method by channel hot electron (CHE) injection is known as an electron injection to cells in flash memories. Here, the CHE write is a method that high energy electrons accelerated over a barrier height of an oxide are injected into a floating gate among channel electrons accelerated by a steep electric field around the drain of memory cells.
Second, an over-erased bit write back by CHE will be described with a cell structure of conventional NOR flash memories. FIG. 28 is a schematic cross-section of a flash memory cell for explanation of a conventional over-erased bit write back by CHE. In FIG. 28, the reference numeral 11 designates a p-type semiconductor substrate; 12a, 12b designate n channel source and drain regions, respectively; 13 is a first gate oxide; 14 designates a floating gate made of polycrystalline silicon or polysilicon and the like; 15 designates a three-layered insulating film of oxide, nitride, and oxide, called xe2x80x98ONOxe2x80x99 for leakage countermeasure; 16 designates a control gate made of polycrystalline silicon and the like; and Vs, Vd, Vcg, and Vsug designate a source voltage, a drain voltage, a control voltage, and a substrate voltage, respectively. Note that the control voltage Vcg is typically set at a higher value than the drain voltage Vd.
A flash memory employing a CHE method is provided with deeply-doped P+ substrate concentration (xcx9c1018 cmxe2x88x923) and N+ diffused layer (xcx9c1020 cmxe2x88x923) in the vicinity of the drain for enhancement of CHE efficiency. For example, FIG. 29 is a graph showing an impurity distribution on the channel surface around the drain edge in a conventional cell structure. This shows a change from decrease to increase after a surface position P0 in which a value of log N plunges. In the conventional cell structure, the CHE efficiency is earned by controlling the expansion of a depletion layer within a p channel substrate region. Referring to the previous Document 1, a drain injection is written As=5xc3x971015 cmxe2x88x922. The N+ diffused layer concentration after thermal treatment or annealing becomes 1020 cmxe2x88x923 or more in such an injection condition.
Next, the operation will be described.
The cell write is performed in such a manner that high energy electrons or CHE accelerated over the barrier height of the first gate oxide 13 are injected into the floating gate 14 among channel electrons accelerated by a steep electric field around the drain. On the other hand, the cell write back may be performed in such a manner that the threshold voltages Vths of over-erased cells are brought to an enhancement condition by the above CHE method.
However, the following difficulties exist in this method.
(1) Since the over-erased cells have to be selected, the circuit configuration becomes complicated.
(2) Since a Vth variation width to be written is different from that of a conventional write, a desired voltage has to be set for drain/gate. That is, this voltage requires another potential disposition which differs from that typically used to bring cells to a write condition.
(3) A channel current has to be driven upon write back operations. (Idxcx9cseveral tens xcexcA/cell)
On the other hand, a write back method using a gate current due to Drain Avalanche Hot Electron (hereinafter abbreviated to DAHE) and Drain Avalanche Hot Hole (hereinafter abbreviated to DAHH) is disclosed as a method without performing bit selections in the write back by the above CHE method (see Document 1).
Hereinafter, a cell structure employing such a write back method will be described.
FIG. 30 is a schematic cross-section of a flash memory cell for explanation of a conventional write back of over-erased bits by DAHE/DAHH. In FIG. 30, the device configuration is substantially the same as the above memory cell by CHE and the description will be omitted. However, there is a difference in a voltage application to electrodes: GND level is applied to Vcg, while GND level or a negative bias is applied to Vsub.
As shown in FIG. 31, the gate current Ig in a cell in flash memories having that drain structure is known in that gate currents specified by DAHH, DAHE, and CHE in turn from a lower side of gate voltages are observed in a gate voltage region in which a channel current flows. This phenomenon is also described in the Document 1 or others (for example, Document 2: IEEE Electron Devices Letter, EDL-7, p.561(1986), Y. Nissan-Cohen, and Document 3: U.S. Pat. No. 5,546,340, Chung-Yu Hu et al.) Here, the gate current of DAHE/DAHH is that among pairs of electrons and holes generated in a high electric field region near the drain together with xe2x80x9cseedxe2x80x9d currents flowing in a channel, the electrons or holes accelerated at a high-energy level in said field are injected into a floating gate. The use of that DAHH/DAHE enables to write back over-erased cells self-convergently.
Hereinafter, evaluations in accordance with this write back method will be described.
A cell structure is employed, which has a sectional configuration in FIG. 32 referring to the aforementioned Document 1. FIG. 34 is a graph showing results that evaluated in a unit cell the write back by this method.
When a cell over-erased up to about 0 V was left on a condition of drain voltage Vd=5 V and control gate voltage Vcg=0 V, the convergence Vth was written back to about 1.75 V. after about 0.1 sec. Thus, the write back method does not require a bit selection which raises an issue in the CHE method, and may be left in such a manner that a drain voltage is applied to all bit lines in an array with a gate voltage of 0 V.
Further, a feature of this method is that even a condition having a Vth higher than the convergence Vth tends to vary toward this convergence Vth. That is, as shown in a graph of gate current characteristics on use of self-convergence in FIG. 31, a cell less than the convergence Vth causes DAHE injection (electron injection) and a floating potential decreases to a value Vg* in the graph. As a result, the cell Vth is written back up to the convergence Vth. On the other hand, a cell more than the convergence Vth causes DAHH injection (hole injection) and the floating potential increases to the value Vg*. As a result, the cell Vth decreases to the convergence Vth. Thus, there is a balance between the DAHE electron injection and the DAHH hole injection in the convergence Vth, that is, both the electron and hole injections continue.
FIG. 35 is a graph showing dependency of drain voltage Vd in the write back method by self-convergence. It is apparent that a time required for the write back increases as drain voltage lowers from Vd=6 V to Vd=4 V.
FIG. 36 is a graph showing gate voltage Vg-drain current Id characteristics in a cell reaching a convergence point, i.e. a convergence vth in the write back method by self-convergence. It is apparent that a current still flows in a written-back cell even in Vg=0 V in FIG. 36. This measurement was performed at Vd=1 V, and a several-xcexcA/bit current could flow upon an actual write back (upon application of Vd=xcx9c5 V). In addition, referring to FIG. 39, it is apparent that a drain current Id of 20 xcexcA (=2xc3x9710xe2x88x925 A) could flow stably in the range of 101 to 102 sec for a write back operation time, which demonstrates current-flowing at the convergence Vth upon write back.
Instead of no selection of bit lines, when the whole array is selected, assuming that an array block size is 256 bits (BL)xc3x972048 bits (WL)=512 kbits and that further a cell current is 1 xcexcA/bit in the convergence Vth, a current of about 500 mA may flow in the write back method. Namely, there is a difficulty with respect to the large amount of driving currents on the write back operation in that method.
It is disclosed that channel conductance deteriorates during write back as a result of DAHE/DAHH gate current (Document 3: IEDM""94, p.291). This is because at the convergence Vth, injections of both electrons and holes are kept through gate oxide, thus deteriorating this oxide itself.
The following prior art is given as references.
FIG. 37 is a cross-section of a semiconductor memory depicted in JP-A 10/144809(1998). In FIG. 37, since a contact structure of N++ region 12bb and P+ region 2b is overlapped with a gate region, electrons and holes generated in a part surrounded by a circle in the drawing are injected into the gate, worsening drain disturb characteristics as shown in FIG. 38. Here, the drain disturb characteristics creates an inconvenience that the Vth goes down when drain voltage upon CHE writing is applied to a cell placed in a high Vth condition for a long time.
One example having no electric field buffer layer in a channel region is a semiconductor memory described in JP-A 4/211178(1992). This demonstrates to converge the Vth in an equivalent point between DAHE/DAHH gate currents. FIG. 39 is a graph showing current convergence characteristics upon the corresponding write back operation. FIG. 39 designates time in the horizontal axis and channel flowing current amount upon write back operation in the vertical axis, and converges a convergence value of about xcx9c10 xcexcA at about 10 sec, which designates an equivalent point between DAHE/DAHH gate currents. Further, the gate oxide broke down at 100 sec. This designates that both electrons and holes are simultaneously injected into the gate oxide, to develop its deterioration and cause its break-down.
Next, an erase sequence will be described as an operating method of a nonvolatile semiconductor memory.
FIG. 33 is a flow chart showing an erase sequence in a conventional NOR flash memory. In FIG. 33, ST11 designates a command input step; ST12 designates a write before erase step; ST13 designates an erase step; and ST14 designates an erase verify step.
When the command input is carried out in the step ST11, all the cells in a block selected once for erasure are written in order to prevent an occurrence of over-erased cells. Conventionally, since it took a long time for that write before erase in the erase sequence, it was difficult to shorten the erase time.
For example, in a NOR cell array to carry out write based on a CHE method, a block of 512 kbits is arranged by an architecture of 256 bits on the same bit line and 2048 bits on the same word line. Assuming that in the write before erase, 32 bits are selected at a time and that the write is performed, the write time at a time is xcx9c20 xcexcsec, it takes 2048/32xc3x97256xc3x9720 xcexcs=0.328 sec for the total erase time.
Accordingly, when a chip having a capacity of 1 Mbits is configured with the above block structure, it takes 0.328 secxc3x972=0.65 sec for just a write before erase operation after erase command input. Though an actual erase time (an operation that brings a cell to a low Vth state) could be shortened to about 0.1 sec when a FN tunnel electric field applied to the oxide on erase was enhanced, it took approximately six times 0.1 sec for only the write before erase to keep an occurrence of over-erased cells.
Though the conventional NOR flash memory is exemplified for explanation in the above, a DINOR flash memory will be described additionally.
FIG. 40 is a schematic cross-section showing a cell structure of a conventional DINOR flash memory. In FIG. 40, since other components are the same as those in FIG. 28 except that the reference numeral 17 designates a lightly doped n-type drain region, i.e. n-drain region, like reference numerals designate identical components or corresponding parts and such description will be omitted.
The DINOR cell structure has the following features, and is different from the NOR one using the CHE write.
(1) An array structure of the DINOR flash memory may be similar to that of the above NOR flash memory.
(2) The write is performed in a low Vth state, while the erase in a high Vth state.
(3) The write operation is performed by applying a positive bias to Vd and a negative bias to Vcg, and extracting electrons from the floating gate to the drain junction region by F-N tunneling in the whole channel.
(4) The erase operation is performed by applying positive bias to Vcg and a negative bias to Vsub, and injecting electrons into the floating gate by F-N tunneling.
In FIG. 42, operation voltages in DINOR flash memories are shown in the table.
Next, a write sequence will be described as a method of operating a non-volatile semiconductor memory.
The write sequence in the conventional DINOR flash memories is shown in a flow chart as shown in FIG. 41. In FIG. 41, ST21 designates a write step; ST22 designates a write verify step; ST23 designates a determining step for determining whether all bits are completed or not; and ST24 designates a write back step.
In operation, since the verify step (ST22) is carried out for each bit in the DINOR memories, the cell Vth does not reach a depletion state more than the NOR memories (over-erased state in the NOR memories, while over-written state in the DINOR memories).
Since a non-volatile semiconductor memory and a method of driving this memory are provided as described above, there are some problems that in the write back using a typical CHE method having gate voltage Vg higher than drain voltage Vd, potential generation different from that on write operation to cells is needed, bit selections of over-erased cells are required, and driving currents are large because of positive flowing of channel currents.
On the other hand, there are some merits that in the write back by self-convergence based on DAHE/DAHH gate currents, no bit selections are required, and also the potential generation may be almost the same setting as that on writing. However, there are some problems caused by the fact that it takes a long time for the convergence once a voltage-down occurs (as a typical example, extension from xcx9c0.1 sec to 1 sec). Thus driving currents on the writeback are large due to convergence currents flowing in the whole array, and the channel conductance of cells is deteriorated.
In addition, since a conventional method of operating a non-volatile semiconductor memory is provided as described above, there are some problems: a difficulty to shorten an erase time due to a long time required for the write before erase so as to control an occurrence of over-erased cells; and an occurrence of over-writing due to an accidentally accelerated write speed.
The present invention has been made to solve the foregoing problems, and it is an object of the present invention to obtain a non-volatile semiconductor memory and methods of driving, operating and manufacturing this memory to be capable of reducing a consumption current and shortening a write back operation time, and further writing back over-erased cells self-covergently and erasing back over-written cells while preventing deterioration of channel conductance.
According to a first aspect of the present invention, there is provided a method of driving a non-volatile semiconductor memory arraying a transistor including: first and second diffused layers of a second conductance type in a semiconductor substrate, opposite to each other through a channel region of a first conductance type; and a two-storied gate electrode having a floating gate and a control gate, formed through a gate insulating film on the channel region of the first conductance type, the method comprising the steps of: setting the channel region of the first conductance type and one of the first and second diffused layers at a first voltage level; setting the other of the first and second diffused layers at a second voltage level; setting the control gate at the first or a third voltage level; and injecting into the floating gate a part of charges flowing in the channel region with respect to the transistor flowing a channel current, based on a setting that a voltage difference between the first voltage level and the second voltage level is larger in absolute value than that between the first voltage level and the third voltage level.
According to a second aspect of the present invention, there is provided a method of driving a non-volatile semiconductor memory arraying a transistor including: first and second diffused layers of a second conductance type in a semiconductor substrate, opposite to each other through a channel region of a first conductance type; and a two-storied gate electrode having a floating gate and a control gate, formed through agate insulating film on the channel region of the first conductance type, the method comprising the steps of: setting the channel region of the first conductance type at a first voltage level; setting one of the first and second diffused layers at a second voltage level; setting the other of the first and second diffused layers at a third voltage level; setting the control gate at the first, second, or a fourth voltage level; injecting into the floating gate a part of charges flowing in the channel region with respect to the transistor flowing a channel current, based on a setting that a voltage difference between the first voltage level and the second voltage level is larger in absolute value than both that between the first voltage level and the third voltage level, and that between the first voltage level and the fourth voltage level.
According to a third aspect of the present invention, there is provided a non-volatile semiconductor memory having a transistor comprising; first and second diffused layers of a second conductance type, opposite to each other through a channel region of a first conductance type in a surface of a semiconductor substrate; a two-storied gate electrode composed of a floating gate and a control gate formed through a gate insulating film on the channel region of the first conductance type; and an electric buffer layer of the second conductance type, formed between at least one of the first and second diffused layers and the channel region, wherein the diffused layer adjacent to the electric field buffer layer does not overlap with the two-storied gate electrode.
According to a fourth aspect of the present invention, there is provided a non-volatile semiconductor memory having a transistor comprising; a first conductance region formed in a surface of a semiconductor substrate of a first conductance type, having a higher concentration than the semiconductor substrate; first and second layers of a second conductance within the first conductance region, opposite to each other through a channel region of a first conductance type; a two-storied gate electrode composed of a floating gate and a control gate formed through a gate insulating film on the channel region of the first conductance type; and an electric buffer layer of the second conductance type, formed within the first conductance region between at least one of the first and second diffused layers and the channel region, wherein the diffused layer adjacent to the electric field buffer layer does not overlap with the two-storied gate electrode.
According to a fifth aspect of the present invention, there is provided a non-volatile semiconductor memory having a transistor comprising; a first conductance region formed in a surface of a semiconductor substrate of a first conductance type, having a higher concentration than the semiconductor substrate; first and second diffused layers of a second conductance type formed within the first conductance region, opposite to each other through a channel region of the first conductance type; a two-storied gate electrode composed of a floating gate and a control gate formed through a gate insulating film on the channel region of the first conductance type; and an electric field buffer layer of the second conductance type, formed within the first conductance region between at least one of the first and second diffused layers and the channel region, wherein the first conductance region is formed by containing the electric field buffer layer and the diffused layer adjacent thereto, and wherein the diffused layer adjacent to the electric field buffer layer does not overlap with the two-storied gate electrode.
Here, the second conductance concentration of the electric field buffer layer is lower than that of the diffused layer adjacent to this buffer layer.
In addition, the transistor is applied to a NOR or DINOR flash memory.
According to a sixth aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory comprising the steps of: forming a first conductance region in a surface of a semiconductor substrate of a first conductance with a higher concentration than the substrate at a predetermined depth; forming a two-storied gate electrode composed of a control gate and a floating gate on the first conductance region through a gate insulating film; forming in the surface a diffused layer of a second conductance type by an impurity injection through a mask of the two-storied gate electrode; forming sidewalls on the two sides of the two-storied gate electrode by anisotropic etching after depositing an insulating film on the whole surface; and forming first and diffused layers of the second conductance type within the range of the predetermined depth by impurity injection through a mask of the two-storied gate electrode and the sidewalls, thereby forming part of the diffused layer into an electric field buffer layer.
According to a seventh aspect of the present invention, there is provided a method of manufacturing a non-volatile semiconductor memory comprising the steps of: forming a two-storied gate electrode composed of a control gate and a floating gate on a semiconductor substrate of a first conductance type through a gate insulating film; forming a diffused layer of a second conductance type in a surface of the substrate by an impurity injection through a mask of the two-storied gate electrode; forming a first conductance region at a predetermined depth by an impurity injection with a higher concentration than the substrate so as to contain at least the diffused layer; forming sidewalls on the two sides of the two-storied gate by anisotropic etching after depositing an insulating film on the whole surface; and forming first and diffused layers of the second conductance within the range of the predetermined depth by an impurity injection through a mask of the two-storied gate electrode and the sidewalls, thereby forming part of the diffused layer into an electric field buffer layer.
Here, the step of forming the first conductance region may be carried out by an injection angle within thirty degrees to a normal line of the substrate.
According to an eighth aspect of the present invention, there is provided a method of operating a non-volatile semiconductor memory having a transistor including: first and second diffused layers of a second conductance type in a surface of a semiconductor substrate, opposite to each other through a channel region of a first conductance type; a two-storied gate electrode having a floating gate and a control gate, formed through a gate insulating film on the channel region of the first conductance type; and an electric field buffer layer of the second conductance type, formed between at least one of the first and second diffused layers and the channel region, wherein the diffused layer adjacent to the electric field buffer layer does not overlap with the two-storied gate electrode, the method comprising the steps of: verifying erase or write performance of the transistor at a predetermined threshold value or less; setting at a first voltage level the channel region of the first conductance type and one of the first and second diffused layers; setting at a second voltage level the other of the first and second diffused layers; setting at a first or third voltage level the control gate; and injecting into the floating gate a part of charges flowing in the channel region with respect to the transistor flowing a channel current, based on a setting that a voltage difference between the first voltage level and the second voltage level is larger in absolute value than that between the first voltage level and the third voltage level.
According to a ninth aspect of the present invention, there is provided a method of operating a non-volatile semiconductor memory having a transistor including: first and second diffused layers of a second conductance type in a surface of a semiconductor substrate, opposite to each other through a channel region of a first conductance type; a two-storied gate electrode having a floating gate and a control gate, formed through a gate insulating film on the channel region of the first conductance type; and an electric field buffer layer of the second conductance type, formed between at least one of the first and second diffused layers and the channel region, wherein the diffused layer adjacent to the electric field buffer layer does not overlap with the two-storied gate electrode, the method comprising the steps of: verifying erase or write performance of the transistor at a predetermined threshold value or less; setting the channel region of the first conductance type at a first voltage level; setting one of the first and second diffused layers at a second voltage level; setting the other of the first and second diffused layers at a third voltage level; setting the control gate at the first, second or a fourth voltage level; and injecting into the floating gate a part of charges flowing in the channel region with respect to the transistor flowing a channel current, based on a setting that a voltage difference between the first voltage level and the second voltage level is larger in absolute value than both that between the first voltage level and the third voltage level and that between the first voltage level and the fourth voltage level.
Here, the operating method may comprises a step of performing a write to the transistor to control an occurrence of an over-erased transistor prior to the verifying step.